Power Electronics Engineer

Remotely
Full-time

Responsibilities  

- Specify and model power stages from 500 W to 200 kW, selecting optimal buck, boost, LLC, and three-phase topologies.  

- Design custom magnetics—planar transformers, coupled inductors, current-sense chokes—and validate with finite-element analysis.  

- Lay out multilayer, high-current PCBs (≤2 mΩ loop resistance) with controlled impedance and Kelvin sensing for accurate regulation.  

- Integrate wide-bandgap MOSFETs and diodes; tune gate-drive circuitry for sub-20 ns switching while mitigating dv/dt stress.  

- Craft digital and analog control algorithms (peak current mode, vector control) on DSP or FPGA platforms.  

- Execute thermal modeling; size heat sinks, vapor chambers, and forced-air paths to maintain junction temps below 125 °C.  

- Conduct compliance testing—EN 55032, CISPR 25, UL/IEC 62368-1—and author technical reports for regulatory bodies.  

- Collaborate with firmware and mechanical teams in an agile, remote-friendly workflow to shorten design cycles.  

- Mentor junior engineers, review schematics, and refine BOMs for cost, reliability, and manufacturability.  


Required Skills  

- 5+ years in power electronics design, prototype to mass production.  

- Mastery of LTspice or PSpice, MATLAB/Simulink, and PLECS.  

- Proficient with oscilloscopes, differential probes, power analyzers, and thermal cameras.  

- In-depth knowledge of GaN and SiC switching behavior, EMI filter synthesis, and control-loop stability (Bode analysis).  

- Proven track record delivering converters meeting >95 % efficiency and <50 mV output ripple.  

- Competence in Altium Designer or Cadence Allegro for high-density PCB layout.  

- Fluent written and spoken English; capable of creating clear design documentation and test plans.  


Preferred Qualifications  

- Experience with bidirectional onboard EV chargers or grid-tied solar inverters.  

- Familiarity with AUTOSAR, ISO 26262, or UL 508C functional-safety workflows.  

- Exposure to digital twin modeling and hardware-in-the-loop validation.