Post-Silicon Hardware Validation Engineer
Key Responsibilities
- Craft and own comprehensive post-silicon validation plans—from requirement breakdown to sign-off reports.
- Develop functional, stress, and corner-case test cases that probe timing, power, and signal-integrity limits.
- Script automated test suites in Python, Tcl, or Perl; trigger continuous lab runs that shrink cycle time.
- Operate high-speed oscilloscopes, logic and protocol analyzers, BERTs, and thermal chambers to collect clean data.
- Characterize silicon across process-voltage-temperature matrices and generate clear statistical dashboards.
- Perform real-time root-cause analysis with JTAG and mixed-signal probes; isolate hardware, firmware, or system issues.
- Collaborate with design, firmware, and manufacturing teams—closing feedback loops and driving design-for-test improvements.
- Author concise validation platforms (custom boards, fixtures, harnesses) that scale across product lines.
- Document findings, flag critical anomalies, and present risk assessments to cross-functional leadership.
Required Qualifications
- Bachelor’s or Master’s in Electrical, Electronics, or Computer Engineering.
- 5+ years hands-on hardware validation or bring-up experience in semiconductors, consumer electronics, automotive, or communications.
- Fluency in Python plus solid C/C++ for low-level debug.
- Proficiency with high-bandwidth test equipment (25 GHz+ scopes, protocol analyzers for PCIe, USB, DDR).
- Deep understanding of digital and mixed-signal fundamentals, clocking, power delivery, and signal integrity.
- Demonstrated ability to analyze large data sets—identify outliers, trends, and actionable insights.
- Clear, concise communicator who converts complex failures into decisive engineering actions.
- Eligibility to work in the United States; ability to collaborate effectively in a hybrid or fully-remote lab-connected setup.
Preferred Extras
- Experience validating 7 nm or below SoCs, RF subsystems, or automotive-grade silicon.
- Knowledge of machine-learning-driven debug or hardware-in-the-loop frameworks.
- Familiarity with safety and compliance standards (AEC-Q100, FCC, CE).
- Track record of publishing whitepapers, patents, or conference presentations on validation methodology.