Digital Design Engineer

Responsibilities

- Translate system requirements into Verilog/VHDL RTL that is fast, compact, and power-aware.  

- Craft reusable architectures and integrate off-the-shelf IP blocks.  

- Conduct synthesis, place-and-route, and static timing analysis to close timing at 500 MHz+.  

- Build self-checking testbenches in SystemVerilog/UVM and automate regression on Linux.  

- Prototype designs on Xilinx or Intel FPGAs, then guide tape-out for 7 nm ASICs.  

- Debug with wave viewers, logic analyzers, and on-chip logic probes.  

- Collaborate with firmware, verification, and board design teams to assure seamless system integration.  

- Document block-level and top-level designs, keeping reviews crisp and data-driven.  

- Mentor junior engineers—code reviews, lunch-and-learns, and pair-debugging.  

Required Skills & Experience

- 5+ years crafting digital logic for production FPGA or ASIC devices.  

- Mastery of Verilog or VHDL plus scripting in Python or TCL.  

- Demonstrated ownership of timing closure and power optimization.  

- Hands-on experience with Synopsys Design Compiler, Cadence Innovus, or equivalent flows.  

- Deep understanding of computer architecture, buses, and high-speed interfaces (PCIe, DDR, Ethernet).  

- Comfortable on Linux command line and with version control (Git, Perforce).  

- Clear communicator able to explain complex trade-offs to non-hardware colleagues.  

Preferred Extras

- Exposure to SystemVerilog Assertions and coverage-driven verification.  

- Knowledge of low-power techniques—clock gating, power-gating, multi-voltage domains.  

- Familiarity with safety-critical DO-254 or automotive ISO 26262 flows.  

- Experience scripting continuous-integration pipelines.  

What You’ll Shape

- Radar processing, machine-learning accelerators, and secure communication cores that must not fail.  

- Rapid FPGA prototypes that de-risk ASIC silicon and reach customers months sooner.  

- IP libraries whose quality sets the bar across the industry.