Analog Design Engineer – Custom IC & Power Management
A well-funded product innovator, we create analog IP blocks that enable smarter wearables, greener power tools, and life-saving diagnostic gear. Our culture prizes scientific curiosity, rigorous data, and agile iteration. You will partner with DSP, firmware, and manufacturing experts across North America and Europe—often asynchronously—to accelerate time-to-market.
Responsibilities
- Design low-noise amplifiers, precision filters, ADC/DAC interfaces, and on-chip power management units from concept to tape-out.
- Build transistor-level schematics in Cadence Virtuoso and verify functionality with HSPICE, LTspice, and MATLAB behavioral models.
- Optimize signal chains for distortion, phase noise, and thermal drift while meeting stringent power budgets.
- Execute full custom layout—matching, shielding, floor-planning—and collaborate with mask design to minimize parasitics.
- Lead mixed-signal verification, integrating digital wrappers and ensuring DFT/DFM compliance.
- Craft comprehensive test plans, direct lab characterization with oscilloscopes, spectrum/network analyzers, and iterate silicon revisions swiftly.
- Author design reviews and mentor junior engineers on best practices and semiconductor physics fundamentals.
Requirements
- Bachelor’s or Master’s in Electrical Engineering or related field; PhD welcome.
- 5+ years hands-on analog IC design in 180 nm to 7 nm CMOS or BiCMOS processes.
- Proficiency with Cadence Virtuoso, Spectre, and industry spice simulators; comfort scripting in Python or MATLAB for automation.
- Deep knowledge of analog circuit theory—bandgap references, op-amp topologies, switched-capacitor networks, sigma-delta converters.
- Proven track record shipping silicon with <-100 dB THD+N, sub-1 µV/√Hz noise floors, or similar performance metrics.
- Sharp debugging skills—EMI mitigation, leakage tracking, ESD robustness, and latch-up prevention.
- Excellent communication; able to distill complex trade-offs to cross-functional, non-technical stakeholders.