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Registration: 29.04.2025

Elisabeth Ramey

Specialization: Digital Design Engineer
VHDL Design Design Engineer
VHDL Design Design Engineer

Skills

ASIC
Verilog
RTL
VHDL
Verilog
SystemVerilog
FPGA

Work experience

Senior Digital Design Engineer
11.2019 - 05.2022 |Qualcomm
ASIC, Verilog, RTL, SystemVerilog, FPGA
● Enhanced existing WIFI PHY emulation model to support various WIFI transactions for MAC-to-MAC emulation.
Senior Digital Design Engineer
10.2019 - 04.2025 |HealthCare
PBI, UART, I2C, GPIO
● Responsible for top-level verification of PBI, UART, I2C, and GPIO peripheral modules. ● Responsibilities include developed test plan and testcases, performed RTL and GLS verification.
Digital Design Engineer
11.2011 - 10.2019 |Precision Optical Transceivers
ASIC, Verilog, RTL
● Responsibilities include developing specifications and microarchitectures. ● Developing test benches and test scenarios at the block level, implementing RTL projects. ● Performing RTL verification at the block level, and performing synthesis at the block level.

Educational background

Computer Engineering
2006 - 2011
University of Minnesota-Twin Cities

Languages

EnglishIntermediate