● Verification Planning: Planned a detailed verification plan covering all design scenarios for functional validation of LAN, RDMA, and MAC flows. ● Environment Architecture: Developed a modular UVM environment from scratch for host to peripheral data flows using parameterized agents for Ready-Valid and AXI-Stream interfaces. ● Constraint Randomization: Developed structured UVM config classes with mapped constraints to ensure consistent CSR configuration. ● Flow Control Verification: Verified Credit based mechanisms by developing custom agents and drivers, utilized randomization to stress test starvation and Head of Line (HoL) blocking scenarios. ● Performance Testing: Ensured design met performance targets by identifying bottlenecks and collaborating with designers on RTL optimization. ● Coverage: Setup and analyzed functional and code coverage metrics to develop targeted stimulus for unverified logic and critical corner cases.

● Test Planning: Developed comprehensive test plans based on PCIe specifications to verify core features. ● TLP Generation: Developed custom VIP sequences for Cfg and Mem TLP generation to validate downstream port and endpoint responses. ● PCIe Ports Modeling: Developed UVM models for PCIe US/DS ports, including Type1 configuration space and memory management for TLP servicing. ● Feature Control: Created constrained randomized classes to manage PF/VF selection, downstream devices and extended capabilities. ● PCIe Feature Support: Added support for and tested multiple PCIe features including SRIOV, ARI, extended capabilities discovery and dynamic BAR allocation. ● Firmware Modeling: Built UVM models to configure design registers (TCAM/BCAM) by parsing in flight enumeration TLPs. ● Design Collaboration: Facilitated rapid defect resolution through daily interaction with designers to debug RTL issues and verify logic fixes.

● Protocol Stimulus: Wrote constraint randomized classes for networking Ethernet header generation to cover various protocol fields. ● AXI VIP and Callbacks: Developed UVM sequences and used callbacks for data sampling and transaction processing. ● Datapath Verification: Validated SmartNIC datapaths by writing targeted sequences and setting up regressions. ● Reference Modeling: Developed UVM scoreboard based on firmware requirements for Match Action processor logic. ● Register Configuration: Configured design APB interfaces using UVM RAL models. ● System Modeling: Integrated DPI-wrapped C models to verify RTL against golden software models. ● CXL Compliance: Ran CXL compliance test suites to verify design adherence to protocol specs.